This invention relates, in general, to a microfabrication process for making enclosed structures, and more particularly to a process for fabricating tunnels, cavities, and similar subsurface structures within a substrate such as a single crystal silicon wafer, to the tunnels, cavities and related enclosed microstructures so fabricated, and to microfabricated devices incorporating such enclosed structures.
Recent developments in micromechanics have successfully lead to the fabrication of microactuators utilizing processes which have involved either bulk or surface micromachining. The most popular surface micromachining process has used polysilicon as the structural layer in which the mechanical structures are formed. In a typical polysilicon process, a sacrificial layer is deposited on a silicon substrate prior to the deposition of the polysilicon layer. The mechanical structures are defined in the polysilicon, and then the sacrificial layer is etched partially or completely down to the silicon substrate to free the structures.
Moving rotors, gears, accelerometers and other structures have been fashioned through the use of the foregoing process to permit relative motion between the structures and the substrate. This process relies on chemical vapor deposition (CVD) to form the alternating layers of oxide and polysilicon and provides significant freedom in device design; however, CVD silicon is usually limited to layers no thicker than 1-2 micrometers.
An alternative process has been the use of bulk micromachining wherein a silicon substrate is etched and sculpted to leave a structure. This has typically been done using wet chemical etchants such as EDP. However, such processes are dependent on the crystal orientation within the silicon substrate so it is difficult to control them. As a result, wet etch processes are not applicable to small (in the range of 1 micron or less) structure definition.
To overcome the disadvantages of the foregoing processes, a reactive ion etching (RIE) process for the fabrication of submicron, single crystal silicon, movable mechanical structures was developed, and is described in U.S. Pat. No. 5,198,390, assigned to the assignee of the present application. That process utilizes multiple masks to define structural elements and metal contacts and permits definition of small, complex structures in single crystal silicon. However, the process required a second lithography step which was difficult to apply to deeper structures because of problems in aligning the second mask. However, the use of single-crystal materials for mechanical structures is beneficial, since these materials have fewer defects, no grain boundaries, and can be scaled to submicron dimensions while retaining their structural and mechanical properties.
A single-mask, low temperature (less than about 300.degree.), self-aligned process for fabricating micron-scale microelectromechanical (MEM) structures was developed from the process described in U.S. Pat. No. 5,198,390, and is described in copending U.S. application Ser. No. 08/312,797, filed Sep. 27, 1994, now U.S. Pat. No. 5,719,073 which is a continuation of U.S. Ser. No. 08/013,319, filed Feb. 4, 1993, (now abandoned), the disclosure of which is hereby incorporated herein by reference. This process, known as "SCREAM I" is a dry bulk micromachining process which uses reactive ion etching to both define and release structures of arbitrary shape and to provide defined metal surfaces on the released structures, as well as on stationary interconnects, pads, and the like. The process permits fabrication of complex shapes, including triangular and rectangular structures, as well as curved structures such as circles, ellipses and parabolas for use in the fabrication of fixed and variable inductors, transformers, capacitors, switches and the like. The structures are released from the underlying substrate in the fabrication process, and can be moved with respect to the substrate.
In accordance with Ser. No. 08/312,797, a single dielectric mask is used to define deep isolating trenches which completely surround defined structures, undercutting the structures to selectively release them and to produce cavities at the bases of surrounding mesas. The released structures are then metallized, with the undercutting and cavity formation breaking the continuity of the deposited metal to thereby electrically isolate the metal on released structures and defined mesas from the metal on the substrate. The low temperature process of the foregoing application allows the process to be carried out on wafers which carry preexisting integrated circuits, and in addition permits the etching of deep, narrow trenches and subsequent deep etching beneath the side walls of the trenches to release defined structures and to produce extended cavities in the side walls surrounding the released structures.
The basic single mask process described in Ser. No. 08/312,797 can be outlined as follows:
First, a dielectric layer of oxide or nitride is deposited on a wafer or substrate, this layer serving as the single mask throughout the remainder of the steps. A standard PECVD process is used because of its high deposition rate and low deposition temperature. Thereafter, resist is spun, exposed and developed on the mask layer. Standard photolithographic resist techniques are used to define the desired beams, pads, interconnects and like structures. Thereafter, the pattern produced in the resist is transferred from the resist to the mask dielectric using, for example, CHF.sub.3 magnetron ion etching (MIE) or RIE.
An O.sub.2 plasma etch may be used to strip the resist layer, and the patterned dielectric mask is then used to transfer the pattern into the underlying wafer to form trenches around the desired structures. A deep vertical reactive ion etch (RIE) or chemically assisted ion beam etch (CAIBE) is required for this purpose. Depending on the choice of structure height, the trenches may be from 4 to over 20 .mu.m deep, with substantially vertical, smooth walls.
After completion of the trenches, a protective conformal layer of PECVD oxide or nitride is applied to cover the silicon beams and other structures to a thickness of about 0.3 .mu.m thick. The conformal dielectric layer covers the top surfaces of the surrounding substrate (or mesa), the defined structures, and the sides and the floor of the trench, so it is necessary to remove the dielectric from the trench floor, as by an anisotropic CF.sub.4 /O.sub.2 RIE at 10 mT. This etch does not require a mask, but removes 0.3 .mu.m of dielectric from the beam and mesa top surfaces and from the trench bottom, leaving the side wall coating undisturbed. As a result, the beam is left with a top surface layer and a side wall layer of dielectric, with the bottom of the trench being film-free.
A deep RIE or CAIBE is then used to etch the trench floor down below the lower edge of the sidewall dielectric. This etch preferably exposes 3 to 5 .mu.m of substrate underneath the dielectric on each side of the beams and under the dielectric on the walls of the surrounding mesa, and it is this exposed substrate under the beams and on the mesa walls which is to be removed during the release step. The release is carried out by an isotropic RIE which etches the substrate out from under the beams or other structures, thus releasing them, and etching the substrate on the mesa walls to form cavities. The etch has high selectivity to the dielectric, allowing several microns of substrate to be etched without appreciably affecting the protective dielectric coating. After release, the beams are held cantilevered over the floor of the deep silicon trench by their connections to the surrounding mesa at their ends, for example.
Each released, cantilevered structure has a core of semiconductor material such as single crystal silicon and a conformal coating of dielectric surrounding it on the top surface and side walls. The structural beams may be cantilevered at both ends and free-floating in the center, or may be cantilevered at one end, with the other end being free-floating, for example. The structure can be activated, as by measuring its motion or by driving it into motion, by applying a voltage to a metal layer. Accordingly, as a final step, an aluminum layer is sputter deposited onto beam top surfaces and side walls, onto the floor of the trenches, and onto the top surface and side walls of the surrounding mesa. The structure is now complete and simply needs to be connected to suitable circuitry to activate it. The circuitry may be on a separate substrate or may be formed in the wafer adjacent the location of the beam prior to fabrication of the beam. It may also be desirable, depending on the application, to add a thin passivation oxide layer 100 to 200 nm thick to prevent shorting between moving structures.
Although the foregoing single mask process has numerous advantages and permits fabrication of a wide variety of microelectromechanical structures or the surfaces of substrates, it has recently been recognized that micron-scale structures located beneath the surface of a substrate would have a wide range of applications. For example, such structures could include micron-scale cavities or tunnels for carrying fluids such as gases or liquids under carefully controlled conditions for use in electrophoresis, ink jet nozzles, and the like. Microfabrication processes for use in producing extremely small and precise mechanical and eletro-mechanical structures have been used in the past to produce enclosed tunnel-like structures in a substrate, but typically such devices have been fabricated through a process of micromachining flow channels on fluid handling regions on the surface of a wafer or other substrate, and then mechanically enclosing the channels by positioning a transparent glass cover over them. However, such devices are difficult to manufacture, since they require precision mechanical alignment of very small components. This is time consuming and expensive, and thus is not entirely satisfactory.